When making an integrated circuit (which may also be referred to as an IC, chip or device), a design layout of the IC is made using, for example, CAD tools. A reticle or mask is then produced for the IC design layout and then photolithography is used to transfer features from the reticle or mask to a die (integrated circuit semiconductor wafer).
Various techniques are used to reduce the level of defects in the resultant die. Significant causes of defects are due to optical effects (especially diffraction) which distort the image of the reticle on the semiconductor wafer. Resolution enhancement technologies (RET) are used to limit this distortion. However, as the scale of features on an IC reduces so the impact of optical effects increases.
In one particular RET, prior to the production of the reticle, the design layout may be optimised using optical proximity correction (OPC) to create an optimised reticle layout as described in U.S. Pat. No. 5,705,301.
Typically, the OPC process involves identification of features that require optimisation. For instance, a rule based approach may be used to find features exhibiting particular properties, e.g. properties that may result in defects when the feature is transferred to the IC wafer. The distortion of features caused by the subsequent manufacturing process, including optical effects may be simulated by the OPC procedure. This could include simulating the optical distortions and diffraction effects occurring when transferring the IC layout design on to an IC wafer. Defects may be identified in the IC layout design should the simulated result fall outside any predetermined tolerances or fail comparison with any other particular criteria. This identification of features requiring optimisation shall be referred to as OPC simulation and may include the rule based tests and/or the manufacturing simulation steps, which are typically performed in OPC processes.
After OPC simulation any features containing defects may be optimised in order to ensure that defects are removed or their effects minimised. As discussed in U.S. Pat. No. 5,705,301 the OPC optimisation stage may use various techniques and amends the physical design layout in order to avoid optical or process distortions, also known as patterning defects, when features are transferred from the reticle or mask that may cause failures of the final device. Where distortions are found that are likely to cause failures the OPC optimisation process discretizes the design layout into moveable segments and manipulates these segments until the distortions are minimised so that the risk of failures in the resultant chip is reduced.
The success of the optimisation of a particular feature may be tested by a further OPC simulation step and the process may iterate until the defects are corrected or minimised.
The OPC procedure may take several iterations and is time consuming and therefore, costly. However, as the critical dimension (CD) of features incorporated into IC designs decreases OPC optimisation must use rules and models of increasing sophistication requiring ever more powerful computer facilities and longer run times to implement.
One alternative RET is known as inverse lithography technology (ILT) or inverse OPC. Such an approach is described in “Inverse Lithography Technology Principles in Practice: Unintuitive Patterns”, Yong Liu, Dan Abrams, Linyong Pang and Andrew Moore, J. Proc. SPIE Vol. 5992, pp 886-893 (2005). Inverse OPC uses a model of the optical system used to transfer the IC design layout onto a semiconductor wafer to create a reticle layout that should form a pattern on the wafer closely matching the layout of the IC layout design itself. In effect, a goal is defined as being the undistorted image and the system is left to run until a pattern is found that would pass through the modelled optical system resulting in a desired image corresponding to the IC design layout or very close to it. Inverse OPC is a highly parallel process which considers large sections of the IC layout design at once.
Inverse OPC can result in reticle layouts that will very accurately produce dies that closely match the required IC layout design. However, inverse OPC can only be used for optimising for optical effects and does not accurately consider other effects such as resist effects, for instance. One major drawback with inverse OPC is that the reticle design that is generated by inverse OPC cannot usually be manufactured successfully due to the complexity or fine structure of the generated reticle designs.